| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2209-509 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L67-1008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L41-0654
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-455
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L67-561
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5055
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3887
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-448 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L12-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-08 |
| filingDate |
2017-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2019-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-107783782-B |
| titleOfInvention |
Compilation for GPU-based parallel processing of node devices |
| abstract |
The present application relates to compilation for GPU-based parallel processing of node devices. An apparatus may include a processor and storage to store instructions that cause the processor to perform operations including: determining whether a task routine can be compiled in response to a determination that a GPU of a node device is available to generate a GPU task routine for execution by the GPU such that multiple instances of tasks of the task routine execute at least partially in parallel with no dependencies therebetween; and responsive to the task routine can be executed via compiling to generate a determination of the GPU task routine: employing a conversion rule to convert the task routine to the GPU task routine; compiling the GPU task routine for execution by the GPU; and converting all Execution of the tasks with respect to dataset partitioning is assigned to the node device to enable execution of the plurality of instances with respect to the dataset partitioning by the GPU. |
| priorityDate |
2016-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |