http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107564955-B
Outgoing Links
Predicate | Object |
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classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7804 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0634 |
classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0834 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-407 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7397 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7394 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K17-567 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7803 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7813 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-739 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
filingDate | 2017-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2020-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationDate | 2020-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | CN-107564955-B |
titleOfInvention | Power semiconductor device with fully depleted channel region and method of operating the same |
abstract | A power semiconductor device having a fully depleted channel region and a method of operating the same. The power semiconductor device (1) comprises: a semiconductor body (10) coupled to a first load terminal structure (11) and a second load terminal structure (12) and configured to conduct a load current (15); a first cell (141) and a second unit (142), each unit being configured to control the load current (15) and each being electrically connected to the first load terminal structure (11) on one side and to the first load terminal structure (11) on the other A drift region (100) electrically connected on one side to a semiconductor body (10); a first mesa (101) included in a first cell (141), which includes a first port region (1011) and a first channel region (1012); a second mesa (102) included in the second cell (142), which includes a second port region (1021) and a second channel region (1022). |
priorityDate | 2016-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.