| Predicate |
Object |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4916 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2017-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-107452738-B |
| titleOfInvention |
Integrated circuit including dummy gate structure and method of forming the same |
| abstract |
The present invention relates to an integrated circuit including a dummy gate structure and a method for forming the same, wherein an integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes: a first gate insulating layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes: a second gate insulating layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is disposed between the first transistor and the second transistor and substantially does not include the high-k dielectric material. |
| priorityDate |
2016-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |