http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107331655-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-945 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-308 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0387 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-92 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-03 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-64 |
| filingDate | 2017-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-107331655-B |
| titleOfInvention | Semiconductor memory and method for forming capacitance profile thereof |
| abstract | The invention provides a semiconductor memory and a capacitor profile forming method thereof. A dielectric layer and a rebound absorbing mask layer are sequentially formed on a substrate, and a plurality of capacitor pattern holes are formed by etching the rebound absorbing mask layer. The pattern hole etches the dielectric layer to form a plurality of capacitor contour holes, and the capacitor contour hole protrudes to the periphery of the capacitor contour hole at a position whose height is 70% to 95% of the total height to form a reaming portion, The maximum aperture of the capacitor profile hole at the reaming portion is less than or equal to 1.2 times the maximum aperture of the capacitor profile hole at the remaining positions. Compared with the capacitor formed in the prior art, the aperture at the reaming portion is reduced. Smaller, the location of the reaming part is increased, so that the outline of the capacitor is more vertical, thereby avoiding the short circuit between the capacitors, and improving the performance of the final formed semiconductor memory. |
| priorityDate | 2017-07-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.