| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0605
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7783
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8252 |
| filingDate |
2011-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-107275287-B |
| titleOfInvention |
Group III-N transistors for system-on-chip (SOC) structures with integrated power management and RF circuits |
| abstract |
System-on-Chip (SoC) solutions for integrating RFICs and PMICs using III-Nitride (III-N) based transistor technology that enables high Ft and also has sufficiently high breakdown voltage (BV) to achieve high voltages and/or high power circuits. In an embodiment, the Group III-N transistor structure is easily scalable to maintain performance improvement routes in many successive device generations. In an embodiment, Group III-N transistor structures are easily monolithically integrated with Group IV transistor structures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments with one or more recessed gates, symmetrical source and drain, regrown source/drain are formed using replacement gate techniques that allow enhancement mode operation and good gate passivation. |
| priorityDate |
2011-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |