Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_62ebc840815e8ac24212643090d1fce4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_00b05982b59e266f9af78cc072cc2c5e |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66803 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02236 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-518 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02323 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02332 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-223 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-423 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
filingDate |
2016-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a47e5f31839954128e570e8b07cb0907 |
publicationDate |
2017-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
CN-107104144-A |
titleOfInvention |
Semiconductor device and manufacturing method thereof |
abstract |
The present disclosure discloses a semiconductor device and a method of manufacturing the same. The method includes: providing a semiconductor structure, the semiconductor structure comprising: a substrate structure; one or more fins protruding from the substrate structure, each fin comprising a germanium layer at least on top of the fin; The dummy gate structure includes: a dummy gate insulator, a dummy gate and a hard mask; and spacers respectively located on both sides of the dummy gate structure; an interlayer dielectric layer is formed on the substrate structure to Cover the dummy gate structure; planarize after forming the interlayer dielectric layer, so that the upper surface of the dummy gate is exposed; remove the dummy gate and dummy gate insulator to expose the surface of the germanium layer underneath; for the germanium layer performing a silane impregnation treatment on the exposed surface of the germanium layer to introduce silicon into the exposed surface of the germanium layer; performing a first oxidation treatment on the exposed surface of the germanium layer into which silicon is introduced to form an oxide layer on the surface of the germanium layer, the oxide layer Contains silicon and germanium. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113363327-A |
priorityDate |
2016-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |