http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107017233-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2607 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2601 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2839 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5256 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0292 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-62 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49838 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0251 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-002 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-34 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-544 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498 |
| filingDate | 2016-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-107017233-B |
| titleOfInvention | Semiconductor devices and its test method and IC chip |
| abstract | Some embodiments of the present invention are related to a kind of semiconductor devices on substrate.Side's setting interconnection structure on substrate, and the first conductive welding disk of side's setting onto the interconnection structure.The setting of second conductive welding disk is square onto the interconnection structure and is spaced apart with the first conductive welding disk.The setting of third conductive welding disk is square onto the interconnection structure and is spaced apart with the first and second conductive welding disks.The setting of 4th conductive welding disk is square onto the interconnection structure and is spaced apart with the first, second, and third conductive welding disk.First ESD protection device is electrically coupled between the first and second pads；And second ESD protection device be electrically coupled between the third and fourth pad.First measured device is electrically coupled between first and third conductive welding disk；And second measured device be electrically coupled to second and the 4th between pad.The embodiment of the present invention further relates to the test method and IC chip of semiconductor devices. |
| priorityDate | 2015-11-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.