| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-45
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M13-611
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1048 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-38 |
| filingDate |
2014-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_70e0e837c83d254ae98ed9abfba1af53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8ad877ca8a822b4adb3678df85585326
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9ee17b2088e2ad4bd4b22c5bcf4a373b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fed5c0f0b697257c00e6841d95a950b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d606f05741163ade4a5b86b77aa7eb63
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b75356531b774dfc07ac60ebdac000e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1c08c1736fad2fc52812e7d2590fb24e |
| publicationDate |
2017-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-107003857-A |
| titleOfInvention |
Apparatus and method for pipeline processing of memory operations with error correction decoding |
| abstract |
The present invention discloses an apparatus and method for pipeline processing of memory operations with error correction decoding. The present invention discloses a method for pipeline processing of consecutive write mask operations, wherein the second read operation of the second write mask operation occurs during the error correction code calculation of the first write mask operation. The method may further include writing data from the first write-masking operation during the error correction code computation of the second write-masking operation. The present invention discloses a method for pipeline processing of consecutive operations, wherein a first read operation can be canceled if said first operation is not a write mask operation. The present invention discloses a device comprising a memory with separate global read and write input-output lines. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110390973-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110390973-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109698001-A |
| priorityDate |
2014-12-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |