http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106415521-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8bb531ac161ea927fd276b48f26bc7af |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D30-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3296 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16 |
| filingDate | 2015-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52b5e8ce76b20245e369c3ff10e45717 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_25f058fcd7f94f48b7d05d051306637e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c2a09934f3413355f66620b8f8eb5f40 |
| publicationDate | 2017-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-106415521-A |
| titleOfInvention | Hardware device and method for multiprocessing dynamic asymmetric and symmetric mode switching |
| abstract | A processing system includes a plurality of processors, wherein a first processor operates at a first clock frequency and a first supply voltage at all times. At least one processor is dynamically switchable to operate at the first clock frequency and the first supply voltage such that the first processor and the second processor provide symmetric multi-processing (SMP), or at Operating at a second clock frequency and a second supply voltage such that the first processor and the second processor provide asymmetrical multi-processing (ASMP). An integrated controller (eg, a finite state-machine (FSM)) controls not only voltage changes, but also clock switching. Various criteria may be used to determine when to switch the at least one switchable processor to improve power consumption and/or performance. After receiving a switching command to switch between SMP and ASMP, a series or series of actions are executed to control the power supply voltage and CPU/memory clock of the switchable processor and cache memory. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110442216-A |
| priorityDate | 2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.