| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a59702f98424f45ab9d74a3710d65b7d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7404
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7436
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-416
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4113
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1027
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8249
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0623 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-411 |
| filingDate |
2015-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e62bc00ce6e8ba756b3e648334d2569b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_459b171a96353df9baaf6ade4c38779a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b4d7b6d9cd7df82f21f5ca42ff878216
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc3fb7a9a24c65aa5d824bb927942a5d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cce505869c50dae46c77c77db1e0fd49 |
| publicationDate |
2016-11-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-106170832-A |
| titleOfInvention |
Cross-coupled thyristor SRAM semiconductor structure and manufacturing method |
| abstract |
A thyristor-based memory cell for an SRAM integrated circuit is illustrated along with a process for fabricating it. The memory cells can be implemented in different combinations of MOS with bipolar select transistors or without select transistors, thyristors in the semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to fabricate the SRAM. Specific circuitry provides reduced power consumption during standby. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11139312-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2021016800-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I699876-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114175274-A |
| priorityDate |
2014-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |