http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106098627-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66272 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8249 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0623 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0817 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0804 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0821 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7371 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8249 |
| filingDate | 2016-04-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-106098627-B |
| titleOfInvention | BiMOS device and its manufacturing method with complete self aligned emitter-silicon |
| abstract | The present invention discloses BiMOS device and its manufacturing method with complete self aligned emitter-silicon.Embodiment provides the method for manufacturing bipolar junction transistor.It is folded the method includes providing the layer heap of the substrate of the first conduction type and arrangement over the substrate, it includes the first separation layer being arranged in the surface district of the substrate, the sacrificial layer being arranged on the first separation layer and the second separation layer being arranged on sacrificial layer that wherein layer heap is folded, wherein layer heap it is folded include by the second separation layer, sacrificial layer and the first separation layer until the surface district of substrate be formed in layer heap it is folded in window.The method further includes providing the collector layer of the first semiconductor type on the substrate within the window that layer heap is folded.The method further includes providing the base layer of the second semiconductor type on the collector layer within the window that layer heap is folded.The method further includes providing emitter layer in the base layer within the window that layer heap is folded or the emitter layer including emitter layer stacks. |
| priorityDate | 2015-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.