http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105988729-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1068 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10 |
| filingDate | 2015-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105988729-B |
| titleOfInvention | Storage system |
| abstract | Embodiments of the present invention provide a kind of storage system that Reliability of Microprocessor can be improved and controller.The storage system of embodiment has semiconductor storage (100) and controller (200).Semiconductor storage (100) can cope with either one or two of the 1st writing mode and the 2nd writing mode.Controller (200) can export the instruction for indicating to correspond among the 1st writing mode and the 2nd writing mode the writing mode of the 1st address to semiconductor storage (100) in the case where receiving to the write instructions of the 1st address. |
| priorityDate | 2014-09-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 26.