| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
| filingDate |
2016-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43b5faec87784151d7cbcff3ca7d05ce
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42ff387fd52712bc46d7d7a549ab1d0a |
| publicationDate |
2016-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-105826325-A |
| titleOfInvention |
Semiconductor device and manufacturing method thereof |
| abstract |
Various embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. Improved reliability of semiconductor devices with nonvolatile memory. The memory cell of the nonvolatile memory is a split gate type, and has a first n-type semiconductor region and a second n-type semiconductor region in a semiconductor substrate, formed between the substrates between the semiconductor regions via a first insulating film and a memory gate electrode formed over the substrate between the first n-type semiconductor region and the second n-type semiconductor region via a second insulating film having a charge accumulating portion. The SSI method is used for writing to memory cells. During a read operation of the memory cell, the first semiconductor region and the second semiconductor region function as a source region and a drain region, respectively. A first width of the first sidewall spacer formed adjacent to a side surface of the memory gate electrode is greater than a second width of a second sidewall spacer formed adjacent to a side surface of the control gate electrode. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107871748-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107871748-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112951833-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112951833-A |
| priorityDate |
2015-01-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |