http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105825895-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31727 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31701 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2601 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-14 |
| filingDate | 2015-07-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105825895-B |
| titleOfInvention | Test mode circuit and semiconductor device including the same |
| abstract | A test mode circuit of a semiconductor device, comprising: a test mode activation signal generating unit adapted to generate a test mode activation signal in response to a test signal; a test clock generation unit adapted to a test clock; a test control signal generating unit, adapted to generate a test control signal based on a plurality of test clocks of the control signal input cycle, wherein the plurality of test clocks have a control signal input cycle and a data input cycle; and an internal control signal generation unit , adapted to generate a plurality of control signals in response to a test control signal and input data to perform a test operation. |
| priorityDate | 2015-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.