http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105514059-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3738 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K7-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-373 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-373 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K7-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-36 |
| filingDate | 2016-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-11-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105514059-B |
| titleOfInvention | A graphene composite material/silicon nitride/silicon chip efficient cooling system |
| abstract | The invention provides a heat dissipation system and construction method based on a graphene composite material/silicon nitride/silicon chip multilayer structure, which belongs to the heat dissipation technology of microelectronic devices. The heat dissipation structure includes a silicon-based heat generating device, a Si 3 N 4 insulating layer, a graphene composite material heat sink and a substrate. Among them, a dense Si 3 N 4 insulating layer is deposited on the back of the silicon wafer by chemical vapor deposition, and the graphene composite material is interconnected with the Si 3 N 4 insulating layer through chemical bonds. The substrates are connected and packaged into devices. The invention utilizes chemical bonds to interconnect silicon-based heating devices, thermal interface materials, and heat sinks, greatly reducing the layer spacing of each device, avoiding thermal resistance caused by interlayer micro-gap, promoting phonon heat transfer, and improving overall heat dissipation The heat dissipation capability of the system enables the chip to work in harsh high-temperature environments. And after packaging, the overall system is lighter and thinner, which is in line with the development trend of contemporary semiconductor devices. |
| priorityDate | 2016-01-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 42.