http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105374833-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14627 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14643 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1463 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14687 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14689 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14685 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 |
| filingDate | 2014-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105374833-B |
| titleOfInvention | Imaging sensor and the method for imaging sensor manufacture |
| abstract | Present application is related to a kind of imaging sensor and the method manufactured for imaging sensor.A kind of imaging sensor includes placement multiple photodiodes in the semiconductor layer and the multiple deep trench isolation regions being placed in the semiconductor layer.The multiple deep trench isolation region includes：(1) oxide skin(coating) is placed on the inner surface of the multiple deep trench isolation region；And (2) conductive filler, it is placed in the multiple deep trench isolation region, wherein the oxide skin(coating) is placed between the semiconductor layer and the conductive filler.Multiple pinning traps are also placed in the semiconductor layer, and the multiple pinning trap combines the individual photodiode in the multiple photodiode of the multiple deep trench isolation region separation.Fixed charge layer is placed on the semiconductor layer, and the multiple deep trench isolation region is placed between the multiple pinning trap and the fixed charge layer. |
| priorityDate | 2014-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.