http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105321950-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 |
| filingDate | 2014-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-105321950-B |
| titleOfInvention | Integrated circuit of embedded flash memory device and method of manufacturing embedded flash memory device |
| abstract | The invention provides an integrated circuit for an embedded flash memory device. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is disposed over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. The flash memory cell device is arranged above the storage area. The flash memory cell device includes a memory cell gate electrically insulated on opposite sides by a corresponding dielectric region. A silicide contact pad is disposed over the top surface of the memory cell gate. A top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and a top surface of the dielectric region. The invention also provides a method for manufacturing the integrated circuit. The present invention relates to recessed salicide structures for integrated flash memory devices and high-κ metal gate logic devices. |
| priorityDate | 2014-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.