| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-26586
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7841
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-315
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 |
| filingDate |
2015-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_12e1fe32bf99d416c8213b3e2bbf8d20 |
| publicationDate |
2016-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-105304724-A |
| titleOfInvention |
Semiconductor device including gate electrode |
| abstract |
A semiconductor device, comprising: a plurality of first gate electrodes buried in a semiconductor substrate including an active region and a device isolation film; a plurality of junction regions including storage node junction regions and storage node junction regions The bit line junction area; a plurality of storage node contact plugs are respectively placed on the storage node junction area and coupled to the storage node junction area; a plurality of storage nodes are respectively placed on the storage node contact plug and coupled to the storage node junction area a storage node contact plug; and a second gate electrode disposed on a sidewall of a corresponding one of the storage node contact plugs. A vertical transistor includes a second gate electrode and a corresponding storage node contact plug, and stores charges leaked from a corresponding one of the storage nodes. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10861855-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109494192-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109494192-B |
| priorityDate |
2014-07-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |