http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105144365-A

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filingDate 2014-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c4faa6723349cad3edc9c0eda07ea94
publicationDate 2015-12-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-105144365-A
titleOfInvention Spacer Enabled Polysilicon Gate
abstract A spacer etch process that produces ultra-narrow polysilicon and gate oxide for insulated gates used with insulated gate transistors. Dielectric and spacer film deposition techniques are used to form narrow channels. The spacer film is removed from the dielectric in which narrow channels are formed. An insulating gate oxide (230a-230d) is grown on the portion of the semiconductor substrate exposed at the bottom of these narrow trenches. Next, polysilicon (232) is used to fill the narrow trenches. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxide and the polysilicon. The very narrow gate oxide and the polysilicon are separated into insulated gates for the insulated gate transistors.
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