http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104835737-B

Outgoing Links

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
filingDate 2014-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2018-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2018-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-104835737-B
titleOfInvention Semiconductor devices and preparation method thereof
abstract The present invention discloses a kind of semiconductor devices and preparation method thereof.This method includes:a)Semiconductor substrate is provided, gate structure is formed in the semiconductor substrate, the semiconductor substrate is interior to be formed with lightly doped region in the both sides of the gate structure;b)Spacer material layer is formed in the semiconductor substrate and the gate structure, the spacer material layer includes the oxide skin(coating) and nitride layer being alternatively formed;c)Dry etching is carried out to the lowermost layer exposed in the spacer material layer to the spacer material layer;d)The nitride layer of oxide skin(coating) or exposing to exposing carries out wet etching, to form side wall in the both sides of the gate structure, wherein remaining oxide skin(coating) and remaining nitride layer have different width;And e)Source and drain doping is carried out to the semiconductor substrate, so as to have doping gradient in the corresponding semiconductor substrate of the side wall.This method effectively reduces hot carrier's effect, enhances MOS device reliability.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/FR-3098978-A1
priorityDate 2014-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 35.