http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104752226-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
| filingDate | 2013-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104752226-B |
| titleOfInvention | The forming method of transistor |
| abstract | The present invention provides a kind of forming method of transistor, including：Substrate is provided, being formed in the substrate surface includes the pseudo- grid structure of pseudo- grid, interlayer dielectric layer is formed on substrate, hard mask layer is covered on interlayer dielectric layer, and photolithographic mask layer is formed on hard mask layer, and by the pattern transfer of photolithographic mask layer into the hard mask layer, to form the opening for exposing pseudo- grid in hard mask layer, photolithographic mask layer is removed, using hard mask layer as mask, the pseudo- grid are removed using pulsed plasma etching, metal gates are formed in the opening that the pseudo- grid of removal are formed.Before pseudo- grid are removed, first remove the photolithographic mask layer above hard mask layer, so that pseudo- grid superstructure only exists hard mask layer, during the pseudo- grid in pseudo- grid structure carry out dry etching, the pollutant on pseudo- grid surface is less, pseudo- grid can be removed totally using the pulsed plasma etching of relatively low etching intensity, avoid damage of the higher etching intensity to interlayer dielectric layer. |
| priorityDate | 2013-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.