| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-70 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-356008
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-35606
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-1733
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C14-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-173
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356 |
| filingDate |
2010-11-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_01586b738d5c3da823a8b306e0b71efa
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8bb761a089dba691e10fe050a316ea73 |
| publicationDate |
2015-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-104700890-A |
| titleOfInvention |
Nonvolatile latch circuits and logic circuits and semiconductor devices using them |
| abstract |
Provided are a new nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit. The latch circuit has a loop structure in which the output of the first element is electrically connected to the input of the second element, and the output of the second element is electrically connected to the input of the first element through the second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and is provided with a capacitor electrically connected to a source electrode or a drain electrode of the transistor, whereby data of a latch circuit can be preserved, and thus a non-conductive circuit can be formed. volatile latch circuit. |
| priorityDate |
2009-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |