| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7685
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3185 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78 |
| filingDate |
2014-10-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2018-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-104600031-B |
| titleOfInvention |
Method for processed wafer |
| abstract |
The present invention provides a kind of methods for processing the chip for including multiple chips.This method may include：In the wafer groove is formed between multiple chips；At least diffusion impervious layer is formed on the side wall of groove；Encapsulating material is formed on multiple chips and in the trench；And from the side individualized multiple chips opposite with encapsulating material. |
| priorityDate |
2013-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |