http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104362176-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78645 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66742 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-772 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2014-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104362176-B |
| titleOfInvention | Self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and manufacturing method thereof |
| abstract | The invention discloses a self-aligned double-gate small-gap semiconductor transistor with high on-off ratio and a manufacturing method thereof. According to the transistor, drain bias voltage is fed back to an auxiliary gate, a clamped square barrier is formed around a drain, and reverse tunneling of drain minority carriers can be well inhibited during running under large bias voltage; thus, the on-off ratio can be increased at the premise of keeping high performance of a non-doped small-gap semiconductor top gate device, and bipolarity is evidently inhibited. Meanwhile, the use of a two-step self-aligned process leads to reduction in device size, and the transistor is applicable to large-scale integrations. |
| priorityDate | 2014-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 52.