http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104217992-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b0a6df6844944a1e86c15955ae218d12 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2013-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_60b74eb88939e41c52488a0ddfb1c925 |
| publicationDate | 2014-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104217992-A |
| titleOfInvention | Semiconductor device and forming method thereof |
| abstract | Disclosed are a semiconductor device and a forming method thereof. The forming method includes: providing a semiconductor substrate, the bottom surface of which is provided with an inter-level dielectric layer, a gate structure comprising a metal gate electrode layer and sidewalls arranged on two sides of the gate structure; removing a certain thickness of the metal gate electrode layer from the gate structure to form an opening; forming a transition metal layer covering the bottom of the opening and allowing exposure of the sidewalls of the opening; forming a cap layer which covers the surface of the transition metal layer and which is flush with the surface of the inter-level dielectric layer; forming a conducting plug penetrating the whole inter-level dielectric layer and electrically connected with both a source region and a drain region. The gate structure and the sidewalls are arranged in the inter-level dielectric layer and are flush with the surface of the inter-level dielectric layer; the source region and the drain region are formed in the semiconductor substrate on two sides of the gate structure. The problem that short circuit between the metal gate electrode layer and the conducting plug affects the performance of a semiconductor device is effectively solved. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116435275-A |
| priorityDate | 2013-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 60.