http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104216680-B

Outgoing Links

Predicate Object
classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-268
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-328
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F8-656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-366
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-22
filingDate 2014-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2019-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2019-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-104216680-B
titleOfInvention Microprocessor and its execution method
abstract A microprocessor and a method of executing the same, the microprocessor including a plurality of processing cores, wherein each of the plurality of processing cores executes microcode and includes hardware for patching the microcode. A first processing core of the plurality of processing cores is configured to: encounter an instruction, wherein the instruction instructs the first processing core to apply a microcode patch; in response to encountering the instruction, notify the microcode patch to the Each of the other processing cores of the above-mentioned plurality of processing cores and the above-mentioned microcode are patched into the above-mentioned hardware of the above-mentioned first processing core. Each processing core of the plurality of processing cores other than the first processing core is configured to apply the microcode patch to the hardware of the processing core in response to the notification of the first processing core. The present invention has less power consumption.
priorityDate 2013-08-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 24.