http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104157699-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-47 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate | 2014-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104157699-B |
| titleOfInvention | A kind of back channel-etch type thin film transistor and preparation method thereof |
| abstract | The present invention relates to a kind of back channel-etch type thin film transistors and preparation method thereof, it is characterised in that: the back channel-etch type thin film transistor using preparation method preparation of the invention includes substrate, gate electrode, gate dielectric layer, active area, source region, drain region, passivation layer, source contact electrode and drain contact electrode；Gate electrode is arranged on substrate, gate dielectric layer is covered on substrate and gate electrode, active area is arranged on gate dielectric layer, source region and drain region are respectively positioned on active area and gate dielectric layer, and are separately positioned on active area two sides, and passivation layer is covered on substrate, gate dielectric layer, active area, source region and drain region, one end of source contact electrode connects source region, the other end of source contact electrode is located on passivation layer, and one end of drain contact electrode connects drain region, and the other end of drain contact electrode is located on passivation layer.The present invention can be widely applied in the preparation process of thin film transistor (TFT) and display panel. |
| priorityDate | 2014-08-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 66.