http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104134697-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7839 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-47 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66969 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1079 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7828 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-47 |
| filingDate | 2014-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104134697-B |
| titleOfInvention | Asymmetric Schottky source drain transistor and preparing method thereof |
| abstract | The invention discloses a ring gate MOS transistor combining a vertical channel and an asymmetric Schottky barrier source/drain structure. The ring gate MOS transistor comprises the ring semiconductor channel (4) in the vertical direction, a ring gate electrode (6), a ring gate dielectric layer (5), a source region (2), a drain region (3) and a semiconductor substrate (1), wherein the source region is located at the bottom of the vertical channel (4) and connected with a substrate, the drain region is located on the top of the vertical channel, the gate dielectric layer and the gate electrode annularly surround the vertical channel, Schottky contacts with different barrier heights can be formed by the source region and the channel and the drain region and the channel respectively, and the source region and the drain region are made of different metal materials. The ring gate MOS transistor is compatible with an existing CMOS technology, various advantages of the traditional GAA are reserved, the leakage current is reduced through the asymmetric Schottky barrier source/drain structure, the technology requirement is lowered, the limitation of processing photoetching extremity is broken through via the vertical channel and the ring gate structure, and the integrity is improved. |
| priorityDate | 2014-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.