http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104078424-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1213 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10K59-1201 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-124 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1237 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-77 |
| filingDate | 2014-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06ab935d9f0a84a2286c78cfa2d6ff4d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_676e80f1c67c752f32f15693acea57be http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ddfb5081d1a199ffbd69915e593a44e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4019aa6fa7736b1e4e70be9fbf049d58 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81158021cca17e180e526ddc8090d0a9 |
| publicationDate | 2014-10-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-104078424-A |
| titleOfInvention | Low-temperature poly-silicon TFT array substrate, manufacturing method thereof and display device |
| abstract | The invention discloses a low-temperature poly-silicon TFT array substrate, a manufacturing method of the low-temperature poly-silicon TFT array substrate and a display device. The manufacturing method comprises the steps that based on the step type photoresist technology, a poly-silicon active layer and a poly-silicon storage capacitor lower electrode plate are formed on the substrate at the same time on the basis of the primary photolithography technique; a gate insulation layer is formed on the poly-silicon active layer and the poly-silicon storage capacitor lower electrode plate; a metal layer is formed on the gate insulation layer, and is etched to form a grid electrode, a grid wire connected with the grid electrode, a source electrode, a drain electrode and a data line connected with the source electrode and the drain electrode; a passivation layer, a photoresist layer and a pixel electrode layer are formed in sequence, picture composition fabrication processing is carried out on the passivation layer, the photoresist layer and the pixel electrode layer, inter-layer insulation layer via holes and patterns of a pixel electrode are formed on the basis of the primary photolithography technique; a pixel definition layer is formed on the pixel electrode. According to the low-temperature poly-silicon TFT array substrate, the manufacturing method of the low-temperature poly-silicon TFT array substrate and the display device, the frequency of the photolithography technique on the low-temperature poly-silicon TFT array substrate is reduced, the technique yield is improved, and technique cost is lowered. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111146239-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/EP-3227913-A4 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108064418-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-105097669-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107658344-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-106298459-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107611171-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110098236-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108288455-A |
| priorityDate | 2014-06-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.