| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-841
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-021 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24 |
| filingDate |
2013-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6ccda3219fc292f368fa6ea7f5e9f47
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cd792273776d4228c5a9c9704bbea919
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eb60fe5da396cce33e84159279887d90
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_601f0a205a3d95444e054e6da66a5c47
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_37f1a0b28e100e3000aa1a5e0710096d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3b91969307291337465347489439a23f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_40cb2856b9ac0fb1c9cad23c98502b1b |
| publicationDate |
2014-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-104051615-A |
| titleOfInvention |
Low form voltage resistive random access memory (rram) |
| abstract |
The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The through hole portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the through hole portion. The invention also provides a low form voltage resistive random access memory (RRAM). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109148682-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107610733-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109273597-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111092153-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107610733-B |
| priorityDate |
2013-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |