| abstract |
The invention provides a manufacturing method and testing method for a chip package of a stereoscopically-stacked integrated circuit system. The manufacturing method comprises the steps that the surface of a first interconnected lead welding pad on the boundary of the surface of a first unpacked chip is exposed; the surface of a second interconnected lead welding pad on the boundary of the surface of a second unpacked chip is exposed; a second dielectric layer on the surface of the second unpacked chip and a first dielectric layer on the surface of the first unpacked chip are bonded; a first semiconductor wafer bonded with the second unpacked chip is electroplated, a cavity is longitudinally filled with an electroplated body from the boundary of the second unpacked chip to form an electroplated electric interconnecting body enabling the first interconnected lead welding pad and the second interconnected lead welding pad to be interconnected vertically and correspondingly. According to the manufacturing method and testing method for the chip package of the stereoscopically-stacked integrated circuit system, wafering of system-in-package, electric interconnection and system testing is achieved, and the manufacturing method and testing method have the advantages of being simple in process, high in integration degree, low in cost and the like. |