http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103872140-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82Y10-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2014-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103872140-B |
| titleOfInvention | A kind of planar rings gate transistor based on nano wire and preparation method thereof |
| abstract | The invention discloses a kind of planar rings gate transistor based on nano wire and preparation method thereof, its structure is：Conducting channel material is parallel to the low-resistance nano wire of substrate；Gate medium and gate electrode radially surround low-resistance nano wire along nano wire successively；Source-drain electrode and gate medium, gate electrode have certain interval at nanowire sidewalls；Source-drain electrode surrounds low-resistance nano wire.The invention also discloses above-mentioned planar rings gate transistor preparation method, gate electrode is first prepared, source-drain electrode is then prepared again；Gate electrode window is initially formed, gate dielectric layer and evaporation gate electrode is grown with atomic layer deposition method, then metal-coated membrane formation source-drain electrode；Low resistance contacts resistance is the method acquisition to intrinsic or low-doped nano wire heavy doping or with metal alloy.The transistor arrangement and preparation method can prepare the shorter device of raceway groove, and effectively reduce parasitic capacitance, strengthen ability of regulation and control of the grid level to raceway groove, so as to improve the performance of device. |
| priorityDate | 2014-03-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 19.