http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103839876-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1005 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1068 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76819 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76865 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2012-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2018-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103839876-B |
| titleOfInvention | The manufacturing method and device of semiconductor devices |
| abstract | The invention discloses the manufacturing methods and device of a kind of semiconductor devices, and to improve the performance of semiconductor devices and reduce the manufacture cost of semiconductor devices, this method includes：Semiconductor base is provided, and sequentially forms dielectric barrier, low-K dielectric matter layer, metal hard mask layer and silicon oxide layer on a semiconductor substrate；Groove and through hole are formed in dielectric barrier, low-K dielectric matter layer, metal hard mask layer and silicon oxide layer；Barrier layer is formed in the top surface and groove of silicon oxide layer and the inner wall of through hole；The deposited metal layer in the top surface and groove and through hole on barrier layer；The metal layer outside groove and through hole and the partial metal layers in groove and through hole are removed using the method for non-stress polishing, the height of the metal layer in groove and through hole is made to be flushed with the top surface of low-K dielectric matter layer；Barrier layer, silicon oxide layer and the metal hard mask layer outside groove and through hole are removed using the method for gas phase etching. |
| priorityDate | 2012-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 52.