| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8833
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0028
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0033 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate |
2011-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2016-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2016-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-103811516-B |
| titleOfInvention |
Three-dimensional nonvolatile memory with asymmetric vertical selection devices |
| abstract |
The present invention provides a non-volatile memory system comprising: a substrate; a monolithic three-dimensional memory array of memory cells defined as being above the substrate and not in the substrate; word lines connected to the memory cells; above the substrate and Multiple vertically oriented bit lines not in substrate, vertically oriented bit lines connected to memory cells; Multiple global bit lines; Multiple asymmetric vertically oriented select devices above and not in substrate, Asymmetric vertically oriented select devices Connected to the vertically oriented bit line and the global bit line, the asymmetric vertically oriented selection device has a first gate interface and a second gate interface; and a plurality of selection lines connected to the selection device, each asymmetric vertically oriented selection device enables One of the select lines is connected to a first gate interface for each asymmetric vertically oriented select device, and the other of the select lines is connected to a second gate interface for each asymmetric vertically oriented select device. |
| priorityDate |
2010-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |