http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103778954-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-413 |
| filingDate | 2014-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2016-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103778954-B |
| titleOfInvention | The memorizer of anti-multiple node upset |
| abstract | The memorizer of anti-multiple node upset, relates to integrated circuit fields.The present invention is to reduce even elimination SEU effect impact in memory.It has the fault-tolerant defencive function when upset of memory element generation single node and multiple node upset, and it includes the stack architecture that two PMOS access transistors and a upper pull-up network and a pulldown network are constituted.The stack architecture (stacked structure) that the upper pull-up network of described one and a pulldown network are constituted, is collectively constituted with nmos pass transistor N1, N2, N3 and N4 by PMOS transistor P1, P2, P3, P4, P5 and P6.Its effect reduces the power consumption of memory element.The present invention can reinforce for the upset of individual node any in memorizer, it is also possible to it is fault-tolerant that two fixing nodes carry out anti-multiple node upset, and does not relies on the value that memorizer is stored. |
| priorityDate | 2014-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578835 |
Total number of triples: 10.