http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103367135-B

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28194
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285
filingDate 2013-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2016-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2016-03-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-103367135-B
titleOfInvention Between gate stack Formation period in the dielectric layer of high dielectric gate pole annealing point defect
abstract This disclosure to relate between gate stack Formation period annealing point defect in the dielectric layer of high dielectric gate pole, substantially improves the technology of the reliability of the semiconductor device having high dielectric constant gate dielectric layer for by annealing point defect between gate stack Formation period.Be disclosed in a demonstration methods herein and comprise the following step: perform the circulation of multiple deposition of material to form dielectric layer with high dielectric constant above semiconductor material layer, and during at least one in the circulation of the plurality of deposition of material, passivating material is introduced the gaseous precursor being used for being formed this dielectric layer with high dielectric constant.
priorityDate 2012-04-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 40.