http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103366793-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1078 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2012-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103366793-B |
| titleOfInvention | SECO in synchronous memories data transfer |
| abstract | The present invention relates to the SECO in synchronous memories data transfer.A kind of solid state memory device, it has memory interface, and the memory interface includes：Clock signal port for receiving clock signal；Data transmission port；Data transmission module, for transmitting block of data signals between data transmission port and memory module；And, selectable delay module, the delay for providing selection between the conversion in the conversion in data-signal DQ and clock signal DQS.The memory interface also has delay controller, it is used for the delay for setting selection, change of the delay relative to reference delay produced by selectable delay module is detected, the pause in the transmission of data-signal DQ blocks is controlled, and the delay of the selection is adjusted in interval. |
| priorityDate | 2012-03-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.