http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103311184-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate | 2012-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2015-11-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103311184-B |
| titleOfInvention | The formation method of transistor, the formation method of CMOS |
| abstract | A formation method for transistor, a kind of formation method of CMOS; Wherein, the formation method of described transistor comprises: provide Semiconductor substrate, described semiconductor substrate surface is formed with gate dielectric layer, gate electrode layer and hard mask layer successively, and described gate dielectric layer, gate electrode layer and hard mask layer both sides are formed with the first side wall and pseudo-side wall successively; Stress liner layer is formed in the Semiconductor substrate of the described pseudo-side wall both sides of next-door neighbour; After formation stress liner layer, remove described pseudo-side wall, then form the second side wall at described first side wall outer surface; After formation second side wall, carry out ion implantation to described stress liner layer, then form self-alignment silicide layer in described stress liner layer, the surface of described self-alignment silicide layer flushes with stress liner layer surface; After formation self-alignment silicide layer, remove described hard mask layer.The formation method of transistor of the present invention can improve the mobility of channel region charge carrier, improves the performance of transistor. |
| priorityDate | 2012-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.