http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-103123901-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41775 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42356 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2012-04-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2016-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2016-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-103123901-B |
| titleOfInvention | The metal gate transistor that N/P boundary effect reduces |
| abstract | The invention provides a kind of method manufacturing semiconductor device.The method is included in types of flexure and forms multiple dummy grid.Dummy grid extends along the first axle.The method is included in above dummy grid and forms mask layer.Mask layer limits the elongated openings extended along the second axle being different from the first axle.Opening exposes first of dummy grid and protects second of dummy grid.The width of the point of opening is greater than the width of the non-point of opening.Optical near-correction (OPC) technique is adopted to form mask layer.The method comprises first with multiple first metal gates replacement dummy grid.The method comprises second with the multiple second metal gates replacement dummy grids being different from the first metal gates.The invention provides the metal gate transistor that N/P boundary effect reduces. |
| priorityDate | 2011-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.