http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102956488-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bddcdc468939a15f15cf5a0809989dc8 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2011-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e4653674c3576aae942aa0920e645c42 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c3b67aca9994835a58dc0dc9a132d08f |
| publicationDate | 2015-02-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-102956488-B |
| titleOfInvention | Power transistor manufacture method |
| abstract | The invention discloses a power transistor manufacture method. By the method, insulating medium layers formed on the top of gate polycrystalline silicon and spacer medium layers formed on the side faces of the insulating medium layers serve as hard masks for etching a pressure-bearing region, so that the number of masks required by the front-side process is decreased, and the density of transistors in a chip can be increased. By the aid of the method, a trench is formed in a P-type well region by etching, and a P-type polycrystalline silicon layer and an N-type polycrystalline silicon layer are filled inside the trench and subjected to annealing to promote formation of a source electrode and a back gate contact region which are longitudinally distributed, so that latching resistance of devices can be improved, and power devices lower in breakover resistance and saturation voltage drop and higher in current driving capacity can be obtained beneficially. |
| priorityDate | 2011-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.