http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102817084-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1e7839224a54a3f4dfc88116c6b4842f |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C30B33-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B81C1-00 |
| filingDate | 2012-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2015-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df858912a4a6fabdfba2809a4db02d00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1aa9786156236148d75d59c1b40b9bac http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_77b86f1ad1c75231678a793a8ede2adb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a17d779fcba9b83122d47abdfbedf5ac |
| publicationDate | 2015-06-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-102817084-B |
| titleOfInvention | Preparation method of silicon nanowire double-layer array structure material |
| abstract | The invention belongs to the technical field of nano-material preparation methods and especially relates to a preparation method of a silicon nanowire double-layer array structure material. The preparation method comprises the following steps of reducing thickness of (100) monocrystalline silicon wafer to below 100 microns by a metal nanoparticle catalytic etching technology, clamping the thin monocrystalline silicon wafer by a Teflon clamp, putting the thin monocrystalline silicon wafer into an etching liquid, and simultaneously carrying out an etching process on an upper surface and a lower surface of the thin monocrystalline silicon wafer with control of a reaction temperature and reaction time to obtain the silicon nanowire double-layer array structure material. The preparation method creatively utilizes etching of upper and lower surfaces of thin monocrystalline silicon wafer to produce the silicon nanowire double-layer array structure material, and realizes control of the thickness of a silicon nanowire double-layer structure by adjustment of the thickness of the thin monocrystalline silicon wafer. The preparation method provided by the invention has a low cost and simple operation processes, is compatible with the existing nanometer device preparation technology, and can reduce a manufacture cost of a novel nanometer device. |
| priorityDate | 2012-08-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.