http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102420106-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_81ca9a5f1da06521982d5a6b55b04244 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-92 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate | 2011-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30ee16df64569669ae8ffdf61b18a366 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_40a0f9a652f3ee7518aab5f275a9a66d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f1e6298dde043c4ded0cf609874b1ef http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_083e559db531e343628fe837b2abfee3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed9cf9212415dfc2e63c717a028fed19 |
| publicationDate | 2013-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-102420106-B |
| titleOfInvention | Metal-insulator-metal capacitor structure and process for manufacturing metal-insulator-metal capacitor structure by adopting copper damascene process |
| abstract | The invention discloses a metal-insulator-metal capacitor structure and a process for manufacturing the metal-insulator-metal capacitor structure by adopting a copper damascene process. The process comprises the following steps of: manufacturing a logic circuit by adopting a dual damascene process, wherein dual-layer metal-insulator-metal comprises three layers of metal electrodes and two intermetallic insulating layers; simultaneously manufacturing a metal interconnected line and a first metal electrode on a matrix dielectric layer by using the damascene process; separately manufacturing a second metal electrode and retaining a dielectric barrier layer on the first metal electrode as a first insulating layer; and simultaneously manufacturing a third metal electrode and a dual damascene structure of the logic circuit and retaining a dielectric barrier layer on the second metal electrode as a second insulating layer. According to the metal-insulator-metal capacitor structure and the process for manufacturing the metal-insulator-metal capacitor structure, disclosed by the invention, the density of the metal-insulator-metal capacitor can be increased; and the metal-insulator-metal capacitor structure and the process for manufacturing the metal-insulator-metal capacitor structure can be completely compatible with the copper dual damascene process of the logic circuit. |
| priorityDate | 2011-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.