http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102347330-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_38ed56a4b4e8e2315b2b3308bffedb3f |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823864 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823468 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823425 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2011-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f59bc4487c8f6f2f733f3316d4e632df http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_63ca43f5a401d4b776be8555f3358475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52de0d49eb322d5c5a38920ace7977fb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75c1b4d617b45830c5282ec94b6941cf http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a5c24aed98558f9a3fd25321c889216 |
| publicationDate | 2013-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-102347330-B |
| titleOfInvention | Semiconductor device and manufacture method thereof |
| abstract | The disclosure relates to a semiconductor device and a manufacture method thereof. The semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width. The semiconductor device is capable of forming interlamination dielectric layers without voids, thereby having improved performance. |
| priorityDate | 2010-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 46.