http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-102292915-B

Outgoing Links

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classificationCPCAdditional http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-742
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-74
filingDate 2010-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2014-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_711861b14790558e1e933eb5e2681f85
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8093f106e12f9e1ba8531c0be0388112
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c6bf8d45f4fdea4d35383499fc12efac
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1960d059ab92f463ae368cd9faee989e
publicationDate 2014-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-102292915-B
titleOfInvention Current switch cell and digital/analog converter
abstract Two D flip-flops (D-FFMA, D-FFMB) divide a digital input signal (DM) into two and output two retimed half-rate signals (DMR-A, DMR-B) by means of a clock signal (CLK) and complementary clock signal (CLKB). A first and second switch (SM1, SM2) are driven by these two half-rate signals (DMR-A, DMR-B), and a third and fourth switch (SM3, SM4) are driven by a select signal (SW) and complementary select signal (SWB) which have the same frequency as the clock signal (CLK) but a different phase. Due to this, a current fed from a current source (1) to a load (4) is made into a current signal corresponding to a converted frequency double the frequency of the clock signal (CLK).
priorityDate 2009-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID454006091

Total number of triples: 20.