| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2223-6677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0248 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-077
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06K19-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate |
2009-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2013-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_eee9961b51571967dc67c5e29fc67329
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89ce31d3641e61d30984549171309fd4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80e7bf29189a56167beaf9ff8bfac472 |
| publicationDate |
2013-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-102057488-B |
| titleOfInvention |
Method for manufacturing semiconductor device |
| abstract |
To provide a simple method for manufacturing a semiconductor device in which deterioration in characteristics due to electrostatic discharge is reduced, a plurality of element layers each having a semiconductor integrated circuit and an antenna are sealed between a first insulator and a second insulator; a layered structure having a first conductive layer formed on a surface of the first insulator, the first insulator, the element layers, the second insulator, and a second conductive layer formed on a surface of the second insulator is formed; and the first insulator and the second insulator are melted, whereby the layered structure is divided so as to include at least one of the semiconductor integrated circuits and one of the antennas. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107479034-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107479034-B |
| priorityDate |
2008-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |