http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-101740499-B
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33cf281df1fdf76b7da1bb88a75ba80d |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-268 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1285 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2026 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-268 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-263 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02 |
| filingDate | 2009-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_581df69fff6637e0d2ae9aac7506c93e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_290a8c84ba7ed8af24855724a8b457cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b2b666e7c49023bdf81c79ce5973a35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8b016e50ec5c3bdf02b9a064d2dcc015 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_49e432cf7af550a3f3d72edb737a377c |
| publicationDate | 2013-05-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-101740499-B |
| titleOfInvention | Array substrate including thin film transistor and method of fabricating the same |
| abstract | A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole. |
| priorityDate | 2008-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.