| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bce787970b69aeb08d159e7c101c9ed7 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C16-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 |
| filingDate |
2006-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2009-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_968a6599d7416feb95ec66ec9287917f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b9aae25b979ab079302ba5cf201ac212
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6c4eac2bb2cfcaa2508c2fd550493592
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c22ace32d60b7c96ed399c4d42098c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_07366d93e26cb0757cc4767e27e21726 |
| publicationDate |
2009-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-100561708-C |
| titleOfInvention |
Make the integration process of stressed transistor structure |
| abstract |
A kind of flow process assembling structure, it uses one or more technology, to control the stress in the semiconductor element that forms thus.According to an embodiment, utilize the RTP (rapid thermal treatment processing procedure) of mononitride separation material and polycrystalline grid and the cumulative stress that deposition constituted of a follow-up heavily stressed etch stop layer, promote strain and improve element function.Also can or implant this grid structure with the germanium deposition to help Stress Control. |
| priorityDate |
2005-05-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |