http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2733667-C
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_713b38aeac59595f1b456b8c1ceb4dfb |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-602 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-755 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-55 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-55 |
| filingDate | 2009-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ca25c232eda284c7d21c1ab3ec03966a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4fa68143a0b361e19b46af7890ba05f4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79db0252289062f77bdaa6b175163612 |
| publicationDate | 2017-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CA-2733667-C |
| titleOfInvention | Method for detecting abnormalities in a cryptographic circuit protected by differential logic, and circuit for implementing said method |
| abstract | The subject of the present invention is a method for detecting anomalies in a circuit protected by differential logic and which processes logic variables represented by a pair of components (at, at), a first network of cells (T) carrying out logic functions on the first component of said pairs, a second network of dual cells (F) operating in complementary logic on the second component, the logic functions being carried out by each pair of cells (T, F) in a pre-charge phase (21) placing the variables in a known state on input to the cells and followed by an evaluation phase (22) where a calculation is performed by the cells, said method being characterized in that an anomaly is detected by at least one non-consistent state. The subject of the invention is also a circuit protected by differential logic comprising means for testing the consistency between the two components of the logic variables during the pre-charge or evaluation phases at the monitored nodes of the circuit. |
| priorityDate | 2008-08-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.