| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f886fa99ff6a230a8d15c2fe724a18e0 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0407
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-14 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3454
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-3459
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-143
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-027 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12 |
| filingDate |
2007-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2010-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bb91579451ac895746efabeaada75d6a |
| publicationDate |
2010-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CA-2649002-C |
| titleOfInvention |
A program verify method for otp memories |
| abstract |
A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data. |
| priorityDate |
2006-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |