http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CA-2635284-C

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filingDate 2007-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2012-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_123b77b9549424cedfd0507094404aff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5a6388f3be4629601ca0c6537233ee9
publicationDate 2012-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CA-2635284-C
titleOfInvention System and method for low power wordline logic for a memory
abstract A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.
priorityDate 2006-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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